HDMI: Is Timing Everything?

We recently showed the timing differences that are so prevalent to Category 5/6 wire products, which can plague HDMI Cat 5/6 extender platform (ATDs) implementation. Timing errors as much as 2700ps (picoseconds) were pretty common among the category cable products we had in the lab.

Some were better than others. Remember, the max limit is about 1500ps, so you tell me if this needs to be addressed? Even more interesting was after interviewing a few of the Category 5 manufacturers we learned that these firms don’t necessarily use a common twist ratio, so one cable can be different from another. This leads to even more variables when it comes to the timing of these signals.

So let’s take a look at Fig 1 (below), which is nothing more than some timing examples of what happens to HDMI TMDS signals when the timing is off. Column A shows raw data coming directly out of an HDMI transmitter located at the output of every source product and A/V receiver. These all should be in perfect time alignment, at least if the manufacturer did its job.

You can see the purple alignment marker is dead center. This means that special attention must be placed with board layout and PCB Trace lengths. Column B is a cable with a fair amount of skew error, but falling within the HDMI specified timing limits, still using the purple line as the alignment mark. When you look at Column C, the errors are so great that it misses the purple alignment mark altogether. Here a product can easily go dark or have severe sparkles and/or color shifting.

But it gets better. Now you have to throw in the fact that Cat 5 ADTs use different wiring schemes. Some opt for 568A and others for 568B, and still others use a pair-by-pair arrangement. This causes even more issues for several reasons. Under 568A pins 3 and 6 split the orange pair, yet under 568B pins 3 and 6 split the green pair. Then you get the pair-to-pair configurations that could be any combination you can think of.

So which pins should be used?

If you consider the timing errors in Fig 1, where the clock channel in column C is so far out, it would be fair to draw a conclusion that the best way to attack this is to choose (interpolate) the one pair that has a skew error between the other three. This would leave the longest twist and the shortest twist within reach of the clock.

Oh, and one more piece of information integrators should consider. Whenever you use a Category 5 extender check to see what wire scheme it was designed for. Any way you look at it, 568 is not recommended; however, most extender firms go there. And by the way, whether it be 568A or 568B they are the same. There is no difference in their integrity as some may claim - due to the fact that when building the printed circuit board traces always have to be bypassed under and over the boards to accommodate the chip sets pin assignments to the crazy pin 3 and 6 split which induces losses.

Always remember that the clock channel is the slowest of all three, typically a tenth of the data rate (HDMI High Speed is 3.4Gbs), which would make it 340MHz. Since this channel is so slow the disturbance on the printed circuit board would have less of an influence on the clock’s integrity. So keeping the clock on the split pair will help with the overall integrity of the install.

To be more proactive, you may want to examine the Cat 5 you’re using and determine the best pair that will keep the clock pair within the minimum reaching distance time-wise to the other three.